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致理科技大學財務金融系


沈劍虹
姓  名:沈劍虹
職  稱:助理教授
最高學歷:台北科技大學電腦與通訊研究所博士
電子信箱:jamesshen10@mail.chihlee.edu.tw
校內分機:4532、4916
研究室位置:忠孝大樓2F研發處產學營運中心
                     財金系辦公室研究室4
主要經歷
致理科技大學財務金融系兼任助理教授
國立台北科技大學兼任助理教授
義隆電子股份有限公司專案副理
普誠科技股份有限公司 資深工程師 
 
著作
期刊論文
  • Y. S. Hwang, J. H. Shen, J. J. Chen, and M.R. Fan, “A THD-Reduction High-Efficiency Audio Amplifier Using Inverter-Based OTAs with Filter-Output Feedback” Microelectronics Journal, vol. 45, no. 1, pp. 102–109, Jan. 2014. (SCI)
  • Y. S. Hwang, J. H. Shen, and J. J. Chen, “A high-efficiency fast-transient-response V2-controlled boost converter with small ESR capacitor’, IET Electronics Letters, Vol. 49, No. 22, pp. 1402-1404, Oct. 2013. (SCI)
  • Y. S. Hwang, J. H. Shen, J. J. Chen, and M.R. Fan, “Performance comparison of integrated fully-differential filterless class-D amplifiers with different feedback techniques,” Analog Integrated Circuits and Signal Processing, vol. 76, no. 2, pp. 167-177, Aug. 2013. (SCI)
  • Y. S. Hwang, J. H. Shen, J. J. Chen, Y. R. Du, and C.C. Yu ,” Implementation of THD-reduction stereo audio amplifier using compensators and sigma–delta modulators,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 1, pp. 243-253, Oct. 2012. (SCI)
     
研討會論文
  • Hong-Yi Huang and Jian-Hong Shen, “A DLL-Based Programmable Clock Generator Using Threshold-Trigger Delay Element and Circular Edge Combiner,” in Proc. IEEE AP-ASIC, Aug. 2004, pp. 76-79. 
  • J. H. Shen and Y. S. Hwang,“ A THD-Reduction Closed-Loop Compensated ΣΔ Class-D Amplifier,” The 21th VLSI Design/CAD Symposium, S10-6, Kaohsiung, Taiwan, Aug. 2010.
 
專利
“DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner,” US 7,292,079, Nov. 6, 2007.
 
教師學術專長與研究領域
AIoT智慧物聯網、程式設計、系統晶片設計