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姓 名：沈劍虹
職 稱：助理教授
最高學歷：台北科技大學電腦與通訊研究所博士
電子信箱：jamesshen10@mail.chihlee.edu.tw
校內分機：4532、4214
研究室位置：財金系辦公室研究室4
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主要經歷
商務管理學院「半導體與智慧製造商務管理微學程」召集人
商務管理學院「智慧金融微學程」召集人
商務管理學院「智慧金融微學程」召集人
國立台北科技大學兼任助理教授
義隆電子股份有限公司專案副理
普誠科技股份有限公司 資深工程師
義隆電子股份有限公司專案副理
普誠科技股份有限公司 資深工程師
著作
期刊論文
- Hien-Chung Lin, Jian-Hong Shen, Shan-Li Chang, Tai-Chih Kuo, Hui-Ling Huang, Cheng-Yi Peter Lin and Hung-Meng Huang, “ Developing a Quick Isolation Bed Inquiry System During the COVID-19 Outbreak: User-Centered Design Approach Based on Toyota Production System” JMIR Formative Research, vol. 9, Oct. 17, 2025.(ESCI)
- Chien-Chung Lin, Jian-Hong Shen, Shu-Fang Chen, Hung-Ming Chen and Hung-Meng, Huang “Developing a Cost-Effective Surgical Scheduling System Applying Lean Thinking and Toyota’s Methods for Surgery-Related Big Data for Improved Data Use in Hospitals: User-Centered Design Approach” JMIR Formative Research, vol. 8, May 24, 2024.(ESCI)
- Y. S. Hwang, J. H. Shen, J. J. Chen, and M.R. Fan, “A THD-Reduction High-Efficiency Audio Amplifier Using Inverter-Based OTAs with Filter-Output Feedback” Microelectronics Journal, vol. 45, no. 1, pp. 102–109, Jan. 2014. (SCI)
- Y. S. Hwang, J. H. Shen, and J. J. Chen, “A high-efficiency fast-transient-response V2-controlled boost converter with small ESR capacitor’, IET Electronics Letters, Vol. 49, No. 22, pp. 1402-1404, Oct. 2013. (SCI)
- Y. S. Hwang, J. H. Shen, J. J. Chen, and M.R. Fan, “Performance comparison of integrated fully-differential filterless class-D amplifiers with different feedback techniques,” Analog Integrated Circuits and Signal Processing, vol. 76, no. 2, pp. 167-177, Aug. 2013. (SCI)
- Y. S. Hwang, J. H. Shen, J. J. Chen, Y. R. Du, and C.C. Yu ,” Implementation of THD-reduction stereo audio amplifier using compensators and sigma–delta modulators,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 1, pp. 243-253, Oct. 2012. (SCI)
研討會論文
- J. H. Shen and Chung Fu Lu,” AI Driven Stock Selection and Investment Strategy: Integrating Fundamental Screening and Technical Indicators” in Proceedings of SITAIBA, Jun. 2026.
- J. H. Shen and Y. S. Hwang,“ A THD-Reduction Closed-Loop Compensated ΣΔ Class-D Amplifier,” The 21th VLSI Design/CAD Symposium, S10-6, Kaohsiung, Taiwan, Aug. 2010.
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Hong-Yi Huang and Jian-Hong Shen, “A DLL-Based Programmable Clock Generator Using Threshold-Trigger Delay Element and Circular Edge Combiner,” in Proc. IEEE AP-ASIC, Aug. 2004, pp. 76-79.
專利
1. 投資決策互動學習系統 新型第M676372號 2025 10月21日
2. 理財知識互動學習系統 新型第M676371號 2025 10月21日
2. 理財知識互動學習系統 新型第M676371號 2025 10月21日
3.“DLL-based programmable clock generator using a threshold-trigger delay element circuit and a circular edge combiner,” US 7,292,079, Nov. 6, 2007.
政府部會計畫案
1. 沈劍虹 (2026) ， 「AI驅動智慧製造品質優化與低碳實作場域精進計畫」，協同主持人，2026/10~2027/09，教育部實作場域設備精進計畫
教師學術專長與研究領域
機器人理財、金融資料分析、AIOT智慧物聯網、人工智慧、系統晶片設計、半導體產業實務